The desired end state of Microelectronics Commons 5G/6G hubs is integrated, resilient, low-latency Command and Control (C2) and communication infrastructure and protocols. Future Generation (5G/6G) radio frequency (RF) technology advancements are critical for the DoD to transition to decentralized, point-of-use, anytime-anywhere RF networks that yield asymmetric DoD warfighting results. The implications of 5G/6G are potentially revolutionary by connecting a wide variety of DoD platforms into a secure network that must remain protected from our adversaries. Future Generation RF connectivity is predicated on secure, efficient and broadband RF microelectronics technology in the RF, microwave, and millimeter-wave (mmW) bands from 0.3-300 GHz. As the complexity and capability of modern warfare grows, facilitated by enablers such as Artificial Intelligence (AI), the amount of data and processing speeds required to support future missions must be bolstered by high bandwidth real-time architecture, highlighted by Joint All Domain Command and Control (JADC2) initiatives. The desired end-state for 5G/6G technology hubs consists of microelectronics solutions addressing 1) disruptive advances in RF power microelectronics for transmit and receive functions in narrow-band, broad-band and high-linearity communications in the RF, microwave, and mmW bands; 2) ultra-efficient RF integrated circuit design topologies delivering communications solutions for power dense systems; 3) software defined networks unconstrained by commercially driven protocols and parameters, resulting in 4) secure, point-of-use, low-latency, and high-speed data rate communications chip-sets capable of integrating terrestrial and non-terrestrial DoD platforms. Future 5G/6G hubs should support agile waveforms and dense, cost-effective scalable networks with ultra-high-speed links to the tactical edge for future autonomous battlespace needs.

Quantum Technology

The desired end-state is a commercial foundry-like access with fast turn-around times. Access to these fabrication facilities, which are amenable to developing process design kits (PDKs) for a variety of leading qubit types and support technologies, should be provided to DoD supported university/academic based collaborators as well as support the U.S. commercial quantum technology industry needs. Subsequently, fast tape-out schedules for academics and industry will both enhance the feedback time for established researchers and open the possibility for new groups or companies to better explore the landscape of qubit chip designs which may be viable for transitions to large scale implementations. The goal is to assist in the development of quantum processor quality and capability as well as quantum sensor and quantum network support. To achieve this end-state, multiple needs must be addressed.

Electromagnetic Warfare

The future of Electromagnetic Warfare (EW) reflects a paradigm shift from the traditional approach of deploying disparate systems to perform singular functions within a rigid spectrum allocation. Modern EW (Radar, Electronic Support Measurers, Electronic Attack, and Electronic Protection) requires rapid deployment of capabilities to outpace the threat using force-level, multi-function systems with ability to sense presence of targets and threats using all of the Electromagnetic Spectrum (EMS). The desired end-state is lab-to-fab maturation of prototypes to support EW, as well as other EMS activities, existing primarily in the application space consuming digitized data from multi-platform sensors and transmitting via programmable multi-function apertures. Hubs will facilitate lab-to-fab maturation of critical microelectronic technologies and applications for transmit, receive, digitization, transport, and processing of received EMS signals for EW missions. Those EM and EMS activities described above are enabled by Domain-Specific Systems-on-Chip (DSSoCs) and discrete chips providing electronic survivability, electronic attack, and electronic support at a wider range of operating frequencies, instantaneous bandwidths, and resolution/bit-depth. All of this must be accomplished with improved form factor and thermal efficiency for DoD to gain technological advantage. There are several EW relevant chip ideas being developed in the commercial sector including, but not limited to, high frequency RF digital to analog converters (DACs/ADCs), RF systems on chip (RFSoCs), digital readout integrated circuits (DROICs), AI-accelerating hardware, high-speed networking, ultra-wide bandgap semiconductors for both RF and power, and simultaneous transmit and receive (STAR) that can bring EW system-level performance down to package scale. While the commercial sector technologies show relevance, additional lab-to-fab maturation efforts of ME and support electronics are required to ensure that technology satisfies stringent military requirements. In addition, military devices often operate at higher power and higher temperatures as compared to those used in the commercial sector. Improvements are required for domestic foundries to support existing high temperature materials and increase the transistor per chip area capability.

Artificial Intelligence (AI) Hardware (HW)

The desired end-state is a fab prototype for eventual deployment in AI-enabled systems for edge applications to enable overmatch performance in operational situation awareness and decision-making in a wide variety of missions. Microelectronics Commons hubs will need to facilitate the lab-to-fab prototyping and testing of these AI hardware platforms.
The exponential growth of data demands advanced data analysis capabilities with higher processing performance, lower energy dissipation, and better system scalability. There is a significant gap between current AI computing capabilities and the vast amount of multi-domain sensor and operational data for high-throughput, low-latency and energy-efficient training and executing (inference) of AI models for data analytics, sensor exploitation and fusion, decision support, autonomy, etc., particularly for systems at the tactical edge where there are strict SWaP constraints. Furthermore, the current state of main-stream AI models and their underlying computing architectures do not enable rapid adaptation to changes in the actual sensor/operational data and environments, leading to degraded real-world performance such as intolerance to subtle changes in inputs (i.e., brittle) and difficulties in transitioning to a new task or environment (i.e., inflexible). Existing AI solutions also lack the appropriate computing architecture/hardware, and subsequently, algorithmic innovations to timely search decision space under complex situations and constraints, generate optimized course-of-action recommendations, and interact-learn-assist the human in decision-making.
Few commercial off-the-shelf hardware options exist today for AI edge applications. Most reduce the time required to train large deep neural networks. These current hardware options fall into two categories. The first involves specialized hardware designs (e.g., Google TPU, Qualcomm NPU) that implement optimized operations for training. The second use neuroscience-inspired designs. For example, neuromorphic chips (e.g., IBM TrueNorth, Intel’s Loihi series) have performed effectively for applications involving mobile robotics, small maritime platforms, and space systems. However, they are not widely available because (1) a strong motivating (commercial) application need has not yet arisen, and (2) further study is needed to increase their performance.
Current industry advances were designed to capture a large consumer base. While they offer flexibility, it often results in lower efficiency and limited ability to tailor the processors to specific applications, architectures, and interfaces. Hubs should facilitate the lab-to-fab prototyping of multiple emerging AI accelerators.

Commercial Leap Ahead

Commercial leap ahead technologies are innovative technologies in which the commercial industry has little to no current business interests that warrant their investment. These leap ahead technologies fall under one of two categories: 1) technologies that provide revolutionary capabilities, and 2) designs of systems that allow us to insert new technologies that will yield dramatically new capabilities.
The desired end state is the lab-to-fab maturation of materials, devices, architectures, and processes to provide and/or enable revolutionary capabilities.

Secure Edge/IOT

The desired end-state of secure edge computing is the prototyping of microelectronics technologies based on lab-to fab transition of novel materials, devices and architectures that enable future mission security and assurance. The rapid proliferation of autonomous systems requires more capable computing technologies to drive the performance, assurance, and resilience needed for the contested threat environments of the future. The integration of these elements into national information systems for edge computing will protect the integrity, confidentiality, and availability of our information systems by preventing the loss of control, exfiltration, or manipulation of our Critical Program Information (CPI), deterring adversaries, and providing a means to react in all circumstances.
Secure processing architectures with varying input/output (I/O), processing capabilities, and size, weight, and power (SWaP) plus security (SWaP+S) constraints are required to meet multiple needs of DoD Industrial Base. The development of a general-purpose secure processing architecture that meets the requirements of many mission threads is a priority with additional architectures developed for more stringent/lenient SWaP+S constraints. Secure edge computing also requires the development of space-targeted secure processors. Secure processing architectures will be designed to utilize state-of-the-art technology that can advance and demonstrate lab-to-fab prototyping, and other fabrication facilities as applicable to air, space, and terrestrial domains. New approaches to edge computing must holistically consider the functionality of the platform.
Properties desirable for secure edge computing include, but are not limited to, 1) advancements in SWaP+S metrics required for future edge computing assets; 2) physical and cyber protection capabilities to provide a holistic security posture to protect the control flow of the processor from external influence, ensure the integrity of the system during execution, prevent exfiltration of information and CPI, and provide a means to recover from threat events; and 3) capabilities to pair secure processors with untrusted high performance computing elements.
It is re-highlighted that peripheral activities pursued as stand-alone topics are not within scope of hubs unless they are essential for lab-to-fab demonstration of the prototype. Some of these activities may include 1) design for testability and verification, 2) innovations and enhancements in cyber and physical defenses, 3) unique modifications to software and algorithms to take advantage of performance and the security features of the hardware components, and 4) new technologies enabling resiliency in operational environments.