NSF –ENABLING ACCESS TO THE SEMICONDUCTOR CHIP ECOSYSTEM FOR DESIGN, FABRICATION, AND TRAINING
The aim of this effort is (i) to dramatically lower the barriers to accessing state-of-the-art electronic design automation (EDA) tools, process design kits (PDKs), and design intellectual property (IP) cores for students and academic researchers, and (ii) to enable students at various levels to design IC chips. A key goal is to broaden participation in IC chip design beyond the small number of institutions currently engaged in these activities.
This effort seeks to establish and manage a community infrastructure that supports the entire IC chip design process beginning from behavior/structural description at the Register Transfer Level (RTL) or above to GDSII fabrication mask file generation. The infrastructure should provide licensing, access, and maintenance of (i) commercial and/or open-source EDA tools necessary for the end-to-end IC chip design and verification process, and (ii) design PDK/IPs at various CMOS technology nodes (potentially including emerging technologies), as well as support for multi-project-chip (MPC) integration. Further, proposals should include efforts to develop, curate, and host educational/tutorial materials on the entire IC chip design flow to help train the next generation of IC designers and researchers.
PROJECT TIMELINE
Solicitation Number: NSF 24-522
Topic Description: NSF expects to fund up to two Chip Design Hub awards under this program
Deadline: April 4th 2024
Sponsor: National Science Foundation
Anticipated Budget: $10,000,000